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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com CS4385 114 db, 192 khz 8-channel d/a converter features z advanced multi-bit delta sigma architecture z 24-bit conversion z automatic detection of sample rates up to 192 khz z 114 db dynamic range z -100 db thd+n z direct stream digital mode ? non-decimating volume control ? on-chip 50 khz filter ? matched pcm and dsd analog output levels z compatible with industry-standard time division multiplexed (tdm) serial interface z selectable digital filters z volume control with 1/ 2-db step size and soft ramp z low clock jitter sensitivity z +5 v analog supply, +2.5 v digital supply z separate 1.8 to 5 v logic supplies for the control & serial ports description the CS4385 is a complete 8-channel digital-to-analog system. this d/a system includes digital de-emphasis, half-db step size volume co ntrol, atapi channel mixing, selectable fast and slow digi tal interpolatio n filters fol- lowed by an oversampled, multi-bit delta sigma modulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. fol- lowing this stage is a multi- element switched capacitor stage and low-pass filter with differential analog outputs. the CS4385 also has a proprietary dsd processor which allows for volume contro l and 50 khz on-chip filter- ing without an intermediate decimation stage. it also offers an optional path for direct dsd conversion by di- rectly using the mu lti-element switched capacitor array. the CS4385 accepts pcm data at sample rates from 4 khz to 216 khz, dsd audio data, and delivers excel- lent sound quality. these features are ideal for multi- channel audio systems including sacd players, a/v re- ceivers, digital tv?s, mi xing consoles, effects processors, sound cards and automotive audio systems. ordering in formation CS4385-cqz -10 to 70 c 48-pin lqfp, lead-free CS4385-dqz -40 to 85 c 48-pin lqfp, lead-free cdb4385 evaluation board i control port supply = 1.8 v to 5 v register/hardware configuration inte rna l v olta ge reference reset s e ria l inte rfa ce level translator level translator tdm serial audio input digital supply = 2.5 v hardware mode or i 2 c/spi software mode control data analog supply = 5 v eight channels of differential outputs 8 8 pcm serial audio input volume controls digital filters switch-cap dac and analog filters multi-bit ? modulators dsd audio in pu t dsd processor -volume control -50 khz filter e xterna l mute control mute signals 2 8 serial audio port supply = 1.8 v to 5 v oct ?04 ds671a1
CS4385 2 ds671a1 table of contents 1. pin description ........................................................................................................... ........ 4 2. characteristics and specifications ........................................................................ 6 specified operating conditions . .............. ................ ............. ............. ............. ........... 6 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 6 dac analog characteristics ....................................................................................... 7 power and thermal characteristics....................................................................... 8 combined interpolation & on-chip analog filter response........................... 9 dsd combined digital and on-chip anal og filter response. ................ ......... 10 digital characteristics ............................................................................................... 11 switching characteristics - pcm ............................................................................. 12 switching characteristics - dsd.............................................................................. 13 switching characteristic s - control port - i 2 c format ................................ 14 switching characteristics - control po rt - spi format ............................... 15 3. applications .............................................................................................................. ........ 18 3.1 master clock .............................................................................................................. ...... 18 3.2 mode select ............................................................................................................... ...... 19 3.3 digital interface formats ................................................................................................ .20 3.3.1 olm #1 ............................................................................................................... 21 3.3.2 olm #2 ............................................................................................................... 22 3.3.3 olm #3 ............................................................................................................... 22 3.3.4 olm #4 ............................................................................................................... 22 3.3.5 tdm .................................................................................................................... 2 3 3.4 oversampling mo des ....................................................................................................... 2 3 3.5 interpolation filter ...................................................................................................... ...... 23 3.6 de-emphasis ............................................................................................................... .... 24 3.7 atapi specification ....................................................................................................... .. 25 3.8 direct stream digital (dsd) mode ............. ...................................................................... 25 3.9 grounding and power supply arrangements .................................................................. 26 3.9.1 capacitor placement ..... ...................................................................................... 27 3.10 analog output and filtering ................. .......................................................................... 27 3.11 the mutec outputs ..................................................................................................... 29 3.12 recommended power-up seq uence ............................................................................. 30 3.12.1 hardware mode ................................................................................................. 30 3.12.2 software mode .................................................................................................. 30 3.13 control port interface ................................................................................................... .. 31 3.13.1 map auto increment ... ...................................................................................... 31 3.13.2 i 2 c mode ........................................................................................................... 31 3.13.3 spi mode .......................................................................................................... 33 3.14 memory address pointer (m ap) .............................................................................. 34 4. register quick reference ......................................................................................... 35 5. register description .................................................................................................... 37 6. parameter definitions .................................................................................................. 49 7. references ................................................................................................................ ........ 49 8. package dimensions ....................................................................................................... 5 0 9. appendix ............ ................ ................ ................ ................. ................ ................ ............ 51
CS4385 ds671a1 3 list of figures figure 1. serial audio interface timing............ ............................................................................ .12 figure 2. tdm serial audio interface timing ...... .......................................................................... 12 figure 3. direct stream digital - serial audio input timing........................................................... 13 figure 4. direct stream digital - serial audio input timing for phase modulation mode.............. 13 figure 5. control port timing - i 2 c format ................................................................................... 14 figure 6. control port timing - spi format...... ............................................................................. 15 figure 7. typical connection diagram, software mode................................................................ 16 figure 8. typical connection diagram, hardware ........................................................................ 17 figure 9. format 0 - left justif ied up to 24-bit data...................................................................... 20 figure 10. format 1 - i 2 s up to 24-bit data................................................................................... 20 figure 11. format 2 - right justif ied 16-bit data .......................................................................... 20 figure 12. format 3 - right justif ied 24-bit data .......................................................................... 20 figure 13. format 4 - right justif ied 20-bit data .......................................................................... 21 figure 14. format 5 - right justif ied 18-bit data .......................................................................... 21 figure 15. format 8 - one line mode 1........................................................................................ 21 figure 16. format 9 - one line mode 2........................................................................................ 22 figure 17. format 10 - one line mode 3...................................................................................... 22 figure 18. format 11 - one line mode 4...................................................................................... 22 figure 19. format 12 - tdm mode................................................................................................ 23 figure 20. de-emphasis curve........................... ........................................................................ .. 24 figure 21. atapi block diagram (x = channel pair 1, 2, 3, or 4) .................................................. 25 figure 22. dsd phase modulation mode diagram .. ...................................................................... 26 figure 23. full-scale output ................................................................................................... ...... 27 figure 24. recommended output filter.............. .......................................................................... 28 figure 25. recommended mute circuitry ........... .......................................................................... 29 figure 26. control port timing, i 2 c mode..................................................................................... 32 figure 27. control port timing, spi mode .................................................................................... 33 figure 28. single speed (fast) stopband rejection ...................................................................... 51 figure 29. single speed (fast) transition band ............................................................................ 51 figure 30. single speed (fast) transition band (detail) ................................................................ 51 figure 31. single speed (fast) passband ripple .......................................................................... 51 figure 32. single speed (slow) stopband rejection..................................................................... 51 figure 33. single speed (slow) transition band........................................................................... 51 figure 34. single speed (slow) transition band (detail)............................................................... 52 figure 35. single speed (slow) passband ripple......................................................................... 52 figure 36. double speed (fast) stopband rejection..................................................................... 52 figure 37. double speed (fast) transition band ........................................................................... 52 figure 38. double speed (fast) transition band (detail)............................................................... 52 figure 39. double speed (fast) passband ripple ......................................................................... 52 figure 40. double speed (slow) stopband rejection ................................................................... 53 figure 41. double speed (slow) transition band ......................................................................... 53 figure 42. double speed (slow) transition band (detail) ............. ................................................ 53 figure 43. double speed (slow) passband ripple ....................................................................... 53 figure 44. quad speed (fast) stopband rejection . ...................................................................... 53 figure 45. quad speed (fast) tr ansition band ............................................................................. 53 figure 46. quad speed (fast) tran sition band (detail) ................................................................. 54 figure 47. quad speed (fast) passband ripple ........................................................................... 54 figure 48. quad speed (slow) st opband rejection...................................................................... 54 figure 49. quad speed (slow) tr ansition band ............................................................................ 54 figure 50. quad speed (slow) transition band (det ail) ................................................................ 54 figure 51. quad speed (slow) pa ssband ripple .......................................................................... 54
CS4385 4 ds671a1 1. pin description pin name # pin description vd 4 digital power ( input ) - positive power supply for the digital se ction. refer to the recommended operat- ing conditions for appropriate voltages. gnd 5 31 ground ( input ) - ground reference. should be connected to analog ground. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. tables 1-3 illustrate several standard audio sample rates and the required master clock frequency. lrck 7 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sdin1 sdin2 sdin3 sdin4 8 11 13 14 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 9 serial clock ( input ) - serial clock for the serial audio interface. vlc 18 control port power ( input ) - determines the required signal level fo r the control port. refer to the rec- ommended operating conditions for appropriate voltages. rst 19 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. filt+ 20 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. requires the capacitive decoupling to analog ground, as shown in the typical connection diagram. sdin3 gnd aoutb2- aouta3+ aoutb3- aoutb2+ va aouta3- aoutb3+ aouta4- aouta4+ 6 2 4 8 10 1 3 5 7 9 11 1 2 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mclk dsdb1 vd sdin1 m4(tst) dsda2 dsda1 gnd sclk sdin2 m3(tst) lrck dsd_sclk dsdb3 dsda3 dsda4 CS4385 dsdb4 vls sdin4 m2(scl/cclk) m1(sda/cdin) vlc rst filt+ vq mutec234 aoutb4- aoutb4+ m0(ad0/cs) aouta2+ aouta2- aoutb1+ aoutb1- aouta1- aouta1+ dsdb2 mutec1
CS4385 ds671a1 5 vq 21 quiescent voltage ( output ) - filter connection for internal quie scent voltage. vq must be capacitively coupled to analog ground, as shown in the typical connection diagram. the nominal voltage level is specified in the analog characteristics and specific ations section. vq presents an appreciable source impedance and any current drawn from this pin wil l alter device performance. however, vq can be used to bias the analog circuitry assuming there is no ac signal component and the dc current is less than the maximum specified in the analog ch aracteristics and specifications section. mutec1 mutec234 41 22 mute control ( output ) - the mute control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clo ck frequency ratio is incorrect. these pins are intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any sin- gle supply system. the use of external mute circuits are not man datory but may be de sired for designs requiring the absolute minimum in extraneous clicks and pops. aouta1 +,- aoutb1 +,- aouta2 +,- aoutb2 +,- aouta3 +,- aoutb3 +,- aouta4 +,- aoutb4 +,- 39, 40 38, 37 35, 36 34, 33 29, 30 28, 27 25, 26 24, 23 differential analog output ( output ) - the full scale differential analog output level is specified in the analog characteristics specification table. va 32 analog power ( input ) - positive power supply for the analog section. refer to the recommended oper- ating conditions for appropriate voltages. vls 43 serial audio interface power ( input ) - determines the required signal level for the serial audio inter- face. refer to the recommended operati ng conditions for appropriate voltages. software mode definitions scl/cclk 15 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i 2 c mode as shown in the typical connection diagram. sda/cdin 16 serial control data ( input/output ) - sda is a data i/o line in i 2 c mode and requires an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram. cdin is the input data line for the control port interface in spi mode. ad0/cs 17 address bit 0 (i 2 c) / chip select (spi) ( input ) - ad0 is a chip address pin in i 2 c mode; cs is the chip select signal for spi format. tst 10 12 test ( input ) - these pins are not used in software mode and should not be left floating (connect to ground). hardware mode definitions m0 m1 m2 m3 m4 17 16 15 12 10 mode selection ( input ) - determines the operational mode of th e device as detailed in tables 4 and 5. dsd definitions dsd_sclk 42 dsd serial clock ( input ) - serial clock for the direct stream digital audio interface. dsda1 dsdb1 dsda2 dsdb2 dsda3 dsdb3 dsda4 dsdb4 3 2 1 48 47 46 45 44 direct stream digital input ( input ) - input for direct stream digital serial audio data. pin name # pin description
CS4385 6 ds671a1 2. characteristics and specifications (all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics an d specifications are derived from measur ements taken at nominal supply voltage and t a = 25 c.) specified operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.25 v v v v specified temperature range -cqz -dqz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 3.2 6.0 6.0 v v v v input current, any pi n except supplies i in -10ma digital input voltage serial data port interface control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t op -55 125 c storage temperature t stg -65 150 c
CS4385 ds671a1 7 dac analog characteristics (full-scale output sine wave, 997 hz (note 1) ; fs = 48/96/192 khz; test load r l = 3 k ? , c l = 100 pf ; measure- ment bandwidth 10 hz to 20 khz, unless otherwise specified. notes: 1. one-half lsb of triangular pdf dither is added to data. 2. performance limited by 16-bit quantization noise. parameters symbol min typ max unit CS4385-cqz dynamic performa nce - all pcm modes and dsd specified temperature range t a -10 - 70 c dynamic range 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 108 105 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise 24-bit 0 db -20 db -60 db 16-bit 0 db (note 2) -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -94 - -45 - - - db db db db db db idle channel noise / signal-to-noise ratio - 114 - db CS4385-dqz dynamic performa nce - all pcm modes and dsd specified temperature range t a -40 - 85 c dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 105 102 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 2) -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -91 - -42 - - - db db db db db db idle channel noise / signal-to-noise ratio - 114 - db
CS4385 8 ds671a1 dac analog character istics - all modes (continued) power and thermal characteristics notes: 3. v fs is tested under load r l and includes attenuation due to z out 4. current consumption increases with increasing fs within a given speed mode and is signal dependant. max values are based on highest fs and highest mclk. 5. i lc measured with no external loading on the sda pin. 6. power down mode is defined as rst pin = low with all clock and data lines held static. 7. valid with the recommended capacitor values on filt+ and vq as shown in figures 7 and 8. parameters symbol min typ max units interchannel isolation (1 khz) -90 -db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c analog output full scale different ial output voltage pcm, dsd processor direct dsd mode v fs 132%?v a 94%?v a 134%?v a 96%?v a 136%?v a 98%?v a vpp vpp output impedance (note 3) z out - 100 - ? max dc current draw from an aout pin i outmax -1.0 -ma min ac-load resistance r l -3 -k ? max load capacitance c l - 100 - pf quiescent voltage v q - 50% v a -vdc max current draw from v q i qmax -10 - a parameters symbol min typ max units power supplies power supply current normal operation, va= 5 v (note 4) vd= 2.5 v interface current, vlc=5 v (note 5) vls=5 v power-down state (all supplies) (note 6) i a i d i lc i ls i pd - - - - - 75 20 2 84 200 83 26 - - - ma ma a a a power dissipation (note 4) va = 5 v, vd = 2.5 v normal operation power-down (note 6) - - 426 1 482 - mw mw package thermal resistance ja jc - - 48 15 - - c/watt c/watt power supply rejection ratio (note 7) (1 khz) (60 hz) psrr - - 60 40 - - db db
CS4385 ds671a1 9 combined interpolation & on-c hip analog filter response the filter characteristics have been normalized to the sample ra te (fs) and can be referenced to the desired sample rate by multiplying the given characteristic by fs.) (see note 12.) notes: 8. slow roll-off interpolation filt er is only available in software mode. 9. response is clock dependent and will scale with fs. 10. for single speed mode, the measurement bandwidth is from stopband to 3 fs. for double speed mode, the measurement bandwidth is from stopband to 3 fs. for quad speed mode, the measurement bandwidth is from stopband to 1.34 fs. 11. de-emphasis is available only in single speed mode; only 44.1 khz de-emphasis is available in hardware mode. 12. amplitude vs. frequency plots of this data are available starting on page 51. parameter fast roll-off unit min typ max combined digital and on-chip analog filt er response - single speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 10) 102 - - db group delay - 10.3/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filter response - double speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 80 - - db group delay - 5.9/fs - s combined digital and on-chip analog filter response - quad speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .635 - - fs stopband attenuation (note 10) 90 - - db group delay - 7.0/fs - s
CS4385 10 ds671a1 combined interpolation & on-c hip analog filter response (cont.) dsd combined digital and on-c hip analog filter response parameter slow roll-off (note 8) unit min typ max single speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 64 - - db group delay - 4.5/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .792 - - fs stopband attenuation (note 10) 70 - - db group delay - 5.3/fs - s quad speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .868 - - fs stopband attenuation (note 10) 75 - - db group delay - 6.4/fs - s parameter min typ max unit dsd processor mode passband (note 9) to -3 db corner 0 - 50 khz frequency response 10 hz to 20 khz -0.05 - +0.05 db roll-off 27 - - db/oct direct dsd mode passband (note 9) to -0.1 db corner to -3 db corner 0 0 - - 26.9 176.4 khz khz frequency response 10 hz to 20 khz -0.1 - 0 db
CS4385 ds671a1 11 digital characteristics 13. any pin except supplies. transient currents of up to 100 ma on the input pins will not cause scr latch- up parameters symbol min typ max units input leakage current (note 13) i in --10 a input capacitance - 8 - pf high-level input voltage serial i/o control i/o v ih v ih 70% 70% - - - - v ls v lc low-level input voltage serial i/o control i/o v il v il - - - - 30% 30% v ls v lc high-level output voltage (i oh = -1.2 ma) control i/o v oh 80% - - v lc low-level output voltage (i ol = 1.2 ma) control i/o v ol --20%v lc mutec auto detect input high voltage v ih 70% - - va mutec auto detect input low voltage v il --30%va maximum mutec drive current i max -3-ma mutec high-level output voltage v oh -va-v mutec low-level output voltage v ol -0-v
CS4385 12 ds671a1 switching charact eristics - pcm ( inputs: logic 0 = gnd, logic 1 = vls, c l = 30pf) notes: 14. after powering up, rst should be held low until after the power supplies and clocks are settled. 15. see tables 1 - 3 on page 18 for suggested mclk frequencies. parameters symbol min max units rst pin low pulse width (note 14) 1-ms mclk frequency 1.024 55.2 mhz mclk duty cycle (note 15) 45 55 % input sample rate - lrck (manual selection) single-speed mode double-speed mode quad-speed mode f s f s f s 4 50 100 54 108 216 khz khz khz input sample rate - lrck (auto detect) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 54 108 216 khz khz khz lrck duty cycle 45 55 % sclk duty cycle 45 55 % sclk high time t sckh 8-ns sclk low time t sckl 8-ns lrck edge to sclk rising edge t lcks 5-ns sclk rising edge to lrck falling edge t lckd 5-ns sdin setup time before sclk rising edge t ds 3-ns sdin hold time after sclk rising edge t dh 5-ns sckh sckl t t sdin1 dh t ds t lcks t lckd t sclk lrck lcks t msb msb-1 sdinx t ds sclk lrck msb t dh t sckh t sckl t lcks msb-1 figure 1. serial audio interface timing figu re 2. tdm serial audio interface timing
CS4385 ds671a1 13 switching charact eristics - dsd (logic 0 = agnd = dgnd; logic 1 = vls volts; c l =20pf) parameter symbol min typ max unit mclk duty cycle 40 - 60 % dsd_sclk pulse width low t sclkl 160 - - ns dsd_sclk pulse width high t sclkh 160 - - ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_a / _b valid to dsd_sclk rising setup time t sdlrs 20 - - ns dsd_sclk rising to dsd_a or dsd_b hold time t sdh 20 - - ns dsd clock to data transition (phase modulation mode) t dpm -20 - 20 ns sclkh t sclkl t dsdxx dsd_sclk sdlrs t sdh t figure 3. direct stream digi tal - serial audio input timing dpm t dsdxx dsd_sclk (64fs) dsd_sclk (128fs) dpm t figure 4. direct stream digita l - serial audio input timing for phase modulation mode
CS4385 14 ds671a1 switching characteristics - control port - i 2 c format (inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 16. data must be held for sufficient time to brid ge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 16) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop s ta rt start stop repeated sda scl t irs rst figure 5. control port timing - i 2 c format
CS4385 ds671a1 15 switching characteristics - co ntrol port - spi format (inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 17. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 18. data must be held for sufficient time to bridge the transition time of cclk. 19. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 17) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 18) t dh 15 - ns rise time of cclk and cdin (note 19) t r2 -100ns fall time of cclk and cdin (note 19) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 6. control po rt timing - spi format
CS4385 16 ds671a1 digital audio source vls mclk vd aouta1+ 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ vq 7 6 lrck sclk sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 sdin4 13 14 analog conditioning and muting aouta1- aoutb1+ 38 37 analog conditioning and muting aoutb1- aouta2+ 35 36 analog conditioning and muting aouta2- aoutb2+ 34 33 analog conditioning and muting aoutb2- aouta3+ 29 30 analog conditioning and muting aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- aouta4+ 25 26 analog conditioning and muting aouta4- aoutb4+ 24 23 analog conditioning and muting aoutb4- mutec1 41 22 mute drive mutec234 11 pcm micro- controller vlc 0.1 f +1.8 v to +5 v 18 dsd audio source 2 48 dsdb2 3 42 dsd_sclk dsda1 dsdb3 dsda3 dsda4 dsdb1 dsda2 46 45 47 1 44 dsdb4 16 15 scl/cclk sda/cdin ado/cs rst 19 17 2 k ? 2 k ? note: necessary for i 2 c control port operation note* CS4385 31 gnd gnd 5 note tst : pins 10, 12 tst* figure 7. typical connection diagram, software mode
CS4385 ds671a1 17 digital audio source vls CS4385 mclk vd aouta1+ 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ vq 7 6 lrck sclk sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 sdin4 13 14 analog conditioning and muting aouta1- aoutb1+ 38 37 analog conditioning and muting aoutb1- aouta2+ 35 36 analog conditioning and muting aouta2- aoutb2+ 34 33 analog conditioning and muting aoutb2- aouta3+ 29 30 analog conditioning and muting aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- aouta4+ 25 26 analog conditioning and muting aouta4- aoutb4+ 24 23 analog conditioning and muting aoutb4- mutec234 22 41 mute drive mutec1 11 pcm 31 gnd gnd 5 stand-alone mode configuration vlc 0.1 f +1.8 v to +5 v 18 dsd audio source 2 48 dsdb2 3 12 m3 dsda1 dsdb3 dsda3 dsda4 dsdb1 dsda2 46 45 47 1 44 dsdb4 16 15 m2 m1 m0 rst 19 17 mute drive 47 k ? optional 42 dsd_sclk 10 m4 figure 8. typical connection diagram, hardware
CS4385 18 ds671a1 3. applications the CS4385 serially accepts twos complement formatted pcm data at standard audio sample rates including 48, 44.1 and 32 kh z in ssm, 96, 88.2 and 64 khz in dsm, and 192, 176.4 and 128 khz in qsm. audio data is inpu t via the serial data input pins (sdinx). the left/right clock (lrck) determines which channel is currently being input on sd inx, and the serial clock (sclk) clocks audio data into the input data buffer. the CS4385 can be config ured in hardware mode by the m0, m1, m2 , m3 and m4 pins and in software mode through i 2 c or spi. 3.1 master clock mclk/lrck must be an int eger ratio as shown in tables 1 - 3. the lrck frequency is equal to fs, the frequency at which words for each channe l are input to the de vice. the mclk-to-lrck frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of mc lk transitions during a single lrck period and by detecting the ab- solute speed of mclk. internal dividers are then set to generate the proper internal clocks. ta- bles 1 - 3 illustrate several standard audio sample rates and the required mclk and lrck frequencies. please note there is no required phase relationship, but mclk, lrck and sclk must be synchronous. sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 1. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 2. double-speed mode standard frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. quad-speed mode standard frequencies = denotes clock ratio and sample rate combin ations which are not supported under auto speed-mode detection. please see ?switc hing characteristics - pcm? on page 12.
CS4385 ds671a1 19 3.2 mode select in hardware mode operation is determined by the m ode select pins. the state of these pins are continually scanned for any changes. these pins require connection to supply or ground as out- lined in figure 8. for m0, m1, m2 supply is vlc and for m3 and m4 supply is vls. tables 4 - 6 show the decode of these pins. in software mode the operational mode and data fo rmat are set in the fm and dif registers. see ?register de scription? on page 37. m1 (dif1) m0 (dif0) description format figure 00 left justified, up to 24-bit data 09 01 i 2 s, up to 24-bit data 110 10 right justified, 16-bit data 211 11 right justified, 24-bit data 312 table 4. pcm digital interface format, hardware mode options m4 m3 m2 (dem) description 00 0 single-speed without de-emphasis (4 to 50 khz sample rates) 00 1 single-speed with 44.1khz de-emphasis; see figure 20 01 0 double-speed (50 to 100 khz sample rates) 01 1 quad-speed (100 to 200 khz sample rates) 10 0 auto speed-mode detect (32khz to 200khz sample rates) 10 1 auto speed-mode detect with 44.1khz de-emphasis; see figure 20 11 x dsd processor mode (see table 6 for details) table 5. mode selection, hardware mode options m2 m1 m0 description 000 64x oversampled dsd data with a 4x mclk to dsd data rate 001 64x oversampled dsd data with a 6x mclk to dsd data rate 010 64x oversampled dsd data with a 8x mclk to dsd data rate 011 64x oversampled dsd data with a 12x mclk to dsd data rate 100 128x oversampled dsd data with a 2x mclk to dsd data rate 101 128x oversampled dsd data with a 3x mclk to dsd data rate 110 128x oversampled dsd data with a 4x mclk to dsd data rate 111 128x oversampled dsd data with a 6x mclk to dsd data rate table 6. direct stream digital (dsd), hardware mode options
CS4385 20 ds671a1 3.3 digital interface formats the serial port operates as a sl ave and supports the i2s, left-jus tified, right-justified, one-line mode (olm) and tdm digital interface formats with varying bit depths from 16 to 32 as shown in figures 9-19. data is clocked into the dac on the rising edge. olm and tdm configurations are only supported in software mode. lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 9. format 0 - left justified up to 24-bit data lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb figure 10. format 1 - i 2 s up to 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 11. format 2 - right justified 16-bit data lrck sclk left channel sdinx 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 12. format 3 - right justified 24-bit data
CS4385 ds671a1 21 3.3.1 olm #1 olm #1 serial audio interface format operates in single, double, or quad-speed mode and will slave to sclk at 128 fs . six channels of msb firs t 20-bit pcm data are input on sdin1. the last two ch annels are input on sdin4. lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 13. format 4 - right justified 20-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 14. format 5 - right justified 18-bit data lrck sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 20 clks 20 clks sdin4 sdin1 dac_a2 dac_a3 dac_a4 dac_b1 dac_b4 dac_b2 dac_b3 figure 15. format 8 - one line mode 1
CS4385 22 ds671a1 3.3.2 olm #2 olm #2 serial audio interface format operates in single, double, or quad-speed mode and will slave to sclk at 256 fs . six channels of msb firs t 24-bit pcm data are input on sdin1. the last two ch annels are input on sdin4. 3.3.3 olm #3 olm #3 serial audio interface format operates in single, double, or quad-speed mode and will slave to sclk at 256 fs. eight channels of msb first 20-bit pcm data are input on sdin1. 3.3.4 olm #4 olm #4 serial audio interface format operates in single, double, or quad-speed mode and will slave to sclk at 256 fs. eight channels of msb firs t 24-bit pcm data are input on sdin1. lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 24 clks 24 clks 128 clks lrck sclk sdin1 sdin4 dac_a4 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 dac_b4 figure 16. format 9 - one line mode 2 lsb msb 20 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 128 clks lrck sclk sdin1 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 lsb msb 20 clks dac_a4 lsb msb 20 clks dac_b4 figure 17. format 10 - one line mode 3 lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 128 clks lrck sclk sdin1 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 lsb msb 24 clks dac_a4 lsb msb 24 clks dac_b4 figure 18. format 11 - one line mode 4
CS4385 ds671a1 23 3.3.5 tdm the tdm serial audio interfac e format operates in sing le, double, or quad-speed mode and will slave to sclk at 256 fs . data is received most signi ficant bit first on the first sclk after an lrck transition and is valid on the rising e dge of sclk. lrck identifies the start of a new fram e and is equal to the sample rate, fs. lrck is sampled as valid on the rising sclk edge preceding the most significant bit of the first data sample and must be held valid for one sclk period. each time slot is 32 bi ts wide, with the valid data sam- ple left justified wit hin the time slot with the re maining bits being zero padded. 3.4 oversampling modes the CS4385 operates in one of three oversampling modes based on t he input sample rate. mode selection is determined by the m4 , m3 and m2 pins in hardware m ode or the fm bits in software mode. single-speed mode supports input sample rates up to 50 khz and uses a 128x oversam- pling ratio. double-speed mode supports input sample rates up to 100 khz and uses an over- sampling ratio of 64x. quad-s peed mode supports input sample rates up to 200 khz and uses an oversampling ratio of 32x. the auto-speed mode detect feature allows for the automatic sele ction of speed mode based off of the incoming sample ra te. this allows the CS4385 to accept a wide range of sample rates with no external intervention neces sary. the auto-speed m ode detect feature is available in both hardware and software mode. 3.5 interpolation filter to accommodate the increasingly complex r equirements of digital audio systems, the CS4385 incorporates selectable in terpolation filters for eac h mode of operation. a ?f ast? and a ?slow? roll- off filter is available in each of single, double, and quad speed modes. these filters have been designed to accommodate a variety of musical tastes and styl es. the filt_sel bit is used to select which filter is used (see the register description section for more details). when in hardware mode, only the ?fas t? roll-off filter is available. filter specifications can be found in section 2, and filter response plot s can be found in figures 28 to 51. dac_b2 lrck sclk lsb msb lsb msb lsb msb lsb msb lsb msb sdin1 dac_a1 dac_a2 dac_b1 dac_a3 256 clks 32 clks 32 clks 32 clks 32 clks 32 clks lsb msb dac_b3 32 clks lsb msb dac_a4 32 clks lsb msb dac_b4 32 clks lsb lsb msb zero data figure 19. format 12 - tdm mode
CS4385 24 ds671a1 3.6 de-emphasis the CS4385 includes on-chip digita l de-emphasis filters. the de-em phasis feature is included to accommodate older audio recordings that utilize pre- emphasis equalization as a means of noise reduction. figure 20 shows t he de-emphasis curve. the freq uency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs if the input sample rate does not match the coefficient wh ich has been selected. in software mode the r equired de-emphasis filter coefficient s for 32 khz, 44.1 khz, or 48 khz are selected via the de-em phasis control bits. in hardware mode only the 44.1 khz coefficient is available (enabl ed through the m2 pin). if the input sample rate is not 44.1 khz and de-empha sis has been selected th en the corner frequen- cies of the de-emphasis filter will be scaled by a factor of the actual fs over 44,100. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 20. de-emphasis curve
CS4385 ds671a1 25 3.7 atapi specification the CS4385 implements the channel mixing functions of the atap i cd-rom specification. the atapi functions are applied per a- b pair. refer to t able 9 on page 46 and figure 21 for addi- tional information. 3.8 direct stream digital (dsd) mode in software mode the dsd/pcm bits (reg. 02h) are used to co nfigure the device for dsd mode. the dsd_dif bits (reg 04h) then control the ex pected dsd rate and mclk ratio. the dir_dsd bit (reg 04h) select s between two proprietary met hods for dsd to analog conver- sion. the first method uses a decimation free dsd processing te chnique which allows for fea- tures such as matched pcm leve l output, dsd volume control, and 50khz on chip filter. the second method sends the dsd data di rectly to the on-chip switched -capacitor filter for conver- sion (without the above mentioned features). the dsd_pm_en bit (reg. 04h) se lects phase modulation (data plus data inverted) as the style of data input. in this mode the dsd_pm_mode bit selects whether a 128fs or 64x clock is used for phase modulated 64x data (see figure 22). use of phase m odulation mode may not directly effect the performance of the CS4385, but may lower the sensitivity to boar d level routing of the dsd data signals. the CS4385 can dete ct errors in the dsd data which does not comply with the sacd specifica- tion. the static_dsd and invalid_dsd bits (r eg. 04h) allow the CS4385 to alter the incom- ing invalid dsd data. depending on the error, the data may either be attenuated or replaced with a muted dsd signal (the mutec pins would be set according to the damute bit (reg. 08h)). ? a channel volume control aout ax aoutbx left chan nel audio d ata right chan nel audio d ata bchannel volume control mute mute sdinx figure 21. atapi bloc k diagram (x = channel pair 1, 2, 3, or 4)
CS4385 26 ds671a1 more information for any of thes e register bits can be found in the register description section. the dsd input structure and analog outputs are designed to h andle a nominal 0 db-sacd (50% modulation index) at full rated performance. signa ls of +3 db-sacd may be applied for brief pe- riods of time however, performance at these le vels is not guaranteed . if sustained +3 db-sacd levels are required, the digital volume control should be set to -3 .0 db. this same volume control register affects pcm output levels. there is no need to change the volume control setting be- tween pcm and dsd in order to ha ve the 0db output levels ma tch (both 0 dbfs and 0 db-sacd will output at -3 db in this case). figure 22. dsd phase modulation mode diagram 3.9 grounding and power supply arrangements as with any high resolution converter, the CS4385 requires careful attentio n to power supply and grounding arrangements if it s potential performance is to be realized. the typical connection di- agram shows the recommended power arrangements, with va, vd , vlc, and vls connected to clean supplies. if the ground pl anes are split between digital ground and analog ground, the gnd pins of the CS4385 sh ould be connected to the analog ground plane. all signals, especially clocks, s hould be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the dac. bcka (128fs) bckd (64fs) dsd_sclk dsdax, dsdbx d1 d1 d1 d0 d2 d2 d0 dsd_sclk dsdax, dsdbx bcka (64fs) dsd_sclk dsd phase modulation mode dsd normal mode not used not used not used
CS4385 ds671a1 27 3.9.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low val- ue ceramic capacitor being the cl osest. to further minimize impedance, these capacitors should be located on the same layer as the da c. if desired, all supply pins with similar voltage ratings may be connected to the same supply, but a decoupli ng capacitor should still be placed on ea ch supply pin. note: all decoupling capacitors should be referenced to analog ground. the cdb4385 evaluation board demonstrates the optimum layout and power supply ar- rangements. 3.10 analog output and filtering the application note ?design notes for a 2-pole filter with differ ential input? discusses the sec- ond-order butterworth filter and differential to singl e-ended converter whic h was implemented on the CS4385 evaluation board, cdb4385 evaluation board, as s een in figure 24. the CS4385 does not include phase or amplit ude compensation for an external filter. therefore, the dac sys- tem phase and amplitude response wi ll be dependent on the exte rnal analog circuitry. the off- chip filter has been des igned to attenuate t he typical full-scale output level to below 2 vrms. figure 23 shows how the full-sca le differential analog output leve l specification is derived. aout+ aout- full-scale output level= (aout+) - (aout-)= 6.7 vpp 3.85 v 2.5 v 1.15 v 3.85 v 2.5 v 1.15 v figure 23. full-scale output
CS4385 28 ds671a1 figure 24. recommended output filter
CS4385 ds671a1 29 3.11 the mutec outputs the mutec1 and mutec234 pins have an auto- polarity detect feature. the mutec output pins are high impedance at the time of reset. the exter nal mute circuitry needs to be self biased into an active state in order to be mu ted during reset. upon release of reset, the CS4385 will detect the status of the mutec pins (hig h or low) and will then select that state as the polarity to drive when the mutes become active. the external-bias voltage level that the mu tec pins see at the time of release of reset must meet the ?mutec auto detect input high/low voltage? specs as out- lined in the digital characteristics section. figure 25 shows a single example of both an active high and an active low mute drive circuit. in these designs, the pull-up and pull-down resistors ha ve been especially chos en to meet the input high/low threshold when used with the mmun 2111 and mmun2211 internal bias resistances of 10 k ? . use of the mute control function is not ma ndatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also , use of the mute control function can en- able the system designer to achieve idle channel noise/signal-to-noi se ratios which are only lim- ited by the external mute circuit. figure 25. recommended mute circuitry
CS4385 30 ds671a1 3.12 recommended power-up sequence 3.12.1 hardware mode 1. hold rst low until the power suppl ies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1. in this state, the registers ar e reset to the default settings , filt+ will remain low, and vq will be connected to va/2. if rst can not be held low long enough the sdinx pins should remain static low until all other clocks are stable, and if possible the rst should be toggled lo w again once the sys- tem is stable. 2. bring rst high. the device wil l remain in a low power state with filt+ low and will ini- tiate the hardware power-up sequence after approximately 512 lrck cycles in single- speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad- speed mode). 3.12.2 software mode 1. hold rst low until the power supply is stable, and the master and lef t/right clocks are locked to the appropriate frequenc ies, as discussed in section 3. 1. in this st ate, the regis- ters are reset to the default settings, filt+ will remain lo w, and vq will be connected to va/2. 2. bring rst high. the device will remain in a lo w power state with filt+ low for 512 lrck cycles in single-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad-speed mode). 3. in order to reduce the chanc es of clicks and pops, perform a write to the cp_en bit prior to the completion of approximately 512 l rck cycles in single -speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-s peed mode). the de- sired register settings can be loaded while keeping the pdn bit se t to 1. if more than the stated number of lrck cycles passes befo re cpen bit is written then the chip will enter hardware mode and begin to oper ate with the m0-m4 as the mode settings. cpen bit may be writt en at anytime, even after the hardwa re sequence has begun. it is advised that if the cpen bit can not be set in time then t he sdinx pins should remain stat- ic low (this way no audio data can be convert ed incorrectly by the hardware mode set- tings). 4. set the pdn bit to 0. this will initiate the power-up s equence, which lasts approximately 50 s.
CS4385 ds671a1 31 3.13 control port interface the control port is used to load al l the internal register settings in order to operate in software mode (see section 5). the operat ion of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i 2 c or spi. 3.13.1 map auto increment the device has map (memory address pointer) aut o increment capabili ty enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for suc- cessive i 2 c writes or reads and spi wr ites. if incr is set to 1, map will auto increment after each byte is written, allowing block reads or writ es of successive registers. 3.13.2 i 2 c mode in the i 2 c mode, data is clocked into and out of the bi-directiona l serial control data line, sda, by the serial control por t clock, scl (see figure 26 for t he clock to data relationship). there is no cs pin. pin ad0 enables the user to alter the chip address (001100[ad0][r/w ]) and should be tied to vlc or gn d as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after pow- er-up, spi mode will be selected. 3.13.2.1 i 2 c write to write to the device, fo llow the procedure below while adhering to the control port switching specificati ons in section 2. 1) initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001100. the se venth bit must match the sett ing of the ad0 pin, and the eighth must be 0. the eighth bit of the address by te is the r/w bit. 2) wait for an acknowledge (ack) from the part, then write to t he memory address pointer, map. this byte points to the register to be written. 3) wait for an acknowledge (a ck) from the part, then write the desire d data to the reg- ister pointed to by the map. 4) if the incr bit (s ee section 3.13.1) is set to 1, r epeat the previous step until all the desired registers are writt en, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c writes to other regist ers are desi red, it is necessary to initiate a repeated start condition and follow the procedure detailed from step 1. if no further writ es to other register s are desired, initiate a stop condition to the bus.
CS4385 32 ds671a1 3.13.2.2 i 2 c read to read from the device, foll ow the procedure bel ow while adhering to the control port switching specifications. 1) initiate a start condition to the i 2 c bus followed by th e address byte. the upper 6 bits must be 001100. the se venth bit must match the sett ing of the ad0 pin, and the eighth must be 1. the eighth bit of the address by te is the r/w bit. 2) after transmitting an ackno wledge (ack), the device will then transmit the contents of the register pointed to by the map. the ma p register will contain the address of the last register written to the map, or the default address (s ee section 3.13.1) if an i 2 c read is the first operation perform ed on the device. 3) once the device has trans mitted the contents of the r egister pointed to by the map, issue an ack. 4) if the incr bit is set to 1, the device will continue to transmit the contents of succes- sive registers. conti nue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c reads from other regist ers are desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from steps 1 a nd 2 from the i 2 c write instructions foll owed by step 1 of the i 2 c read section. if no further reads from other registers are desired , initiate a stop condition to the bus. sda scl 001100 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 26. control port timing, i 2 c mode
CS4385 ds671a1 33 3.13.3 spi mode in spi mode, data is clocked into the serial control dat a line, cdin, by the serial control port clock, cclk (see figure 27 fo r the clock to data relationsh ip). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all si gnals are inputs and data is clocked in on the rising edge of cclk. 3.13.3.1 spi write to write to the device, fo llow the procedure below while adhering to the control port switching specifications in section 2. 1) bring cs low. 2) the address byte on the cd in pin must then be 00110000. 3) write to the memory address pointer, ma p. this byte points to the register to be writ- ten. 4) write the desired data to the register pointed to by the map. 5) if the incr bit (s ee section 3.13.1) is set to 1, r epeat the previous step until all the desired registers are wr itten, then bring cs high. 6) if the incr bit is set to 0 and further sp i writes to other regi sters are desired, it is necessary to bring cs high, and follow the procedure detaile d from step 1. if no further writes to other regist ers are desired, bring cs high. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0011000 figure 27. control po rt timing, spi mode
CS4385 34 ds671a1 3.14 memory address pointer (map) 3.14.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 3.14.2 map4-0 (memory address pointer) default = ?00000? 76543210 incr reserved reserved map4 map3 map2 map1 map0 00000000
CS4385 ds671a1 35 4. register quick reference addr function 7 6 5 4 3 2 1 0 01h chip revision part4 part3 part2 part1 part0 rev rev rev default 00001 x x x 02h mode control cpen freeze dsd/pcm dac4_dis dac3_dis dac2_dis dac1_dis pdn default 00 0 00001 03h pcm control dif3 dif2 dif1 dif0 reserved reserved fm1 fm0 default 00000011 04h dsd control dsd_dif2 dsd_dif1 dsd_dif0 dir_dsd static_d sd invalid_d sd dsd_pm_ md dsd_pm_ en default 00001100 05h filter control reserved reserved reserved r eserved reserved reserved reserved filt_sel default 00000000 06h invert control inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 00000000 07h group control reserved mutec reserved p1_a=b p2_a=b p3_a=b p4_a=b snglvol default 00100100 08h ramp and mute szc1 szc0 rmp_up rmp_dn pamute damute mute_p1 mute_p0 default 10000000 09h mute control mute_b4 mute_a4 mute_b3 mute_a3 mute_b2 mute_a2 mute_b1 mute_a1 default 00000000 0ah mixing control pair 1 (aoutx1) reserved p1_dem1 p1_dem0 p1atapi4 p1a tapi3 p1atapi2 p1atapi1 p1atapi0 default 00101001 0bh vol. control a1 a1_vol7 a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 00000000 0ch vol. control b1 b1_vol7 b1_vol6 b1_vol 5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 00000000 0dh mixing control pair 2 (aoutx1) reserved p2_dem1 p2_dem0 p2atapi4 p2a tapi3 p2atapi2 p2atapi1 p2atapi0 default 00101001 0eh vol. control a2 a2_vol7 a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 00000000 0fh vol. control b2 b2_vol7 b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 00000000 10h mixing control pair 3 (aoutx1) reserved p3_dem1 p3_dem0 p3atapi4 p3a tapi3 p3atapi2 p3atapi1 p3atapi0 default 00101001 11h vol. control a3 a3_vol7 a3_vol6 a3_vol 5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 00000000 12h vol. control b3 b3_vol7 b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 00000000 13h mixing control pair 4 (aoutx1) reserved p4_dem1 p4_dem0 p4atapi4 p4a tapi3 p4atapi2 p4atapi1 p4atapi0 default 00101001
CS4385 36 ds671a1 14h vol. control a4 a4_vol7 a4_vol6 a4_vol5 a4_vol4 a4_vol3 a4_vol2 a4_vol1 a4_vol0 default 00000000 15h vol. control b4 b4_vol7 b4_vol6 b4_vol5 b4_vol4 b4_vol3 b4_vol2 b4_vol1 b4_vol0 default 00000000 16h pcm clock mode reserved reserved mclkdiv r eserved reserved reserved reserved reserved default 00000000 addr function 7 6 5 4 3 2 1 0
CS4385 ds671a1 37 5. register description note: all registers are read/write in i 2 c mode and write only in spi, unless otherwise noted. 5.1 chip revision (address 01h) 5.1.1 part number id (part) [read only] 00001- CS4385 revision id (rev) [read only] 000 - revision a function: this read-only register can be used to identif y the model and revision number of the device. 5.2 mode control 1 (address 02h) 5.2.1 control port enable (cpen) default = 0 0 - disabled 1 - enabled function: this bit defaults to 0, allowing the device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the registers and the pin definitions will conform to control port mode. to accomplish a clean power- up, the user should write this bit within 10 ms following the release of reset. 76543210 part4 part3 part2 part1 part0 rev2 rev1 rev0 00001 - - - 76543210 cpen freeze dsd/pcm dac4_dis dac3_dis dac2_dis dac1_dis pdn 00 0 00001
CS4385 38 ds671a1 5.2.2 freeze controls (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to the registers without the changes taking effect until the freeze is disabled. to make mu ltiple changes in the control port registers take effect simulta- neously, enable the freeze bit, make all register changes, then disable the freeze bit. 5.2.3 pcm/dsd selection (dsd/pcm ) default = 0 0 - pcm 1 - dsd function: this function selects dsd or pcm mode. the appropriate data and clocks should be present before changing modes, or else mute should be selected. 5.2.4 dac pair disable (dacx_dis) default = 0 0 - enabled 1 - disabled function: when enabled the respective dac channel pair x (aoutax and aoutbx) will re main in a reset state. it is advised that changes to these bits be made wh ile the power down bit is enabled to eliminate the possibility of audible artifacts. 5.2.5 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a low-power state when th is function is enabled, and the conten ts of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation in control port mode can occur.
CS4385 ds671a1 39 5.3 pcm control (address 03h) 5.3.1 digital interface format (dif) default = 0000 - format 0 ( left justified, up to 24-bit data ) function: these bits select the interface format for the serial audio input. the dsd/pcm bit determines whether pcm or dsd mode is selected. the required relationship between the left/right clock, se rial clock and serial data is defined by the digital interface format and the options are detailed in figures 9-19. 5.3.2 functional mode (fm) default = 11 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - auto speed mode detect (3 2 khz to 200 khz sample rates) function: selects the required range of input sample rates or auto speed mode. 76543210 dif3 dif2 dif1 dif0 reserved reserved fm1 fm0 00000011 dif3 dif2 dif1 dif0 description format figure 0000 left justified, up to 24-bit data 09 0001 i 2 s, up to 24-bit data 110 0010 right justified, 16-bit data 211 0011 right justified, 24-bit data 312 0100 right justified, 20-bit data 413 0101 right justified, 18-bit data 514 1000 one-line mode 1, 24-bit data +sdin4 815 1001 one-line mode 2, 20-bit data +sdin4 916 1010 one-line mode 3, 24-bit 6-channel 10 17 1011 one-line mode 4, 20-bit 6-channel 11 18 1100 tdm 12 19 xxxx all other combinations are reserved table 7. digital interface formats - pcm mode
CS4385 40 ds671a1 5.4 dsd control (address 04h) 5.4.1 dsd mode digital interface format (dsd_dif) default = 000 - format 0 ( 64x oversampled dsd data with a 4x mclk to dsd data rate ) function: the relationship between the oversampling ratio of th e dsd audio data and the required master clock to dsd data rate is defined by the digital interface format pins. the dsd/pcm bit determines whether pcm or dsd mode is selected. 5.4.2 direct dsd conversion (dir_dsd) function: when set to 0 (default), dsd input data is sent to the dsd processor for filtering and volume control func- tions. when set to 1, dsd input da ta is sent directly to the switched ca pacitor dacs for a pure dsd conversion. in this mode the full scale dsd and pcm levels will not be matched (see sect ion 2), the dynamic range performance may be reduced, the volu me control is inactive, and the 50 kh z low pass filter is not available (see section 2 for filter specifications). 5.4.3 static dsd detect (static_dsd) function: when set to 1 (default), the dsd processor checks fo r 28 consecutive zeroes or ones and, if detected, sends a mute signal to the dacs. the mutec pins will eventually go active according to the damute register. when set to 0, this function is disabled. 76543210 dsd_dif2 dsd_dif1 dsd_dif0 dir_dsd stati c_dsd invalid_dsd dsd_pm_md dsd_pm_en 00001100 dif2 dif1 difo description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate 0 0 1 64x oversampled dsd data with a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data with a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 8. digital interface formats - dsd mode
CS4385 ds671a1 41 5.4.4 invalid dsd detect (invalid_dsd) function: when set to 1, the dsd proc essor checks for greater than 24 out of 28 bits of the same value and, if de- tected, will attenuate th e data sent to the dacs. the mutec pi ns go active according to the damute register. when set to 0 (default), this function is disabled. 5.4.5 dsd phase modulation mode select (dsd_pm_mode) function: when set to 0 (default), the 128fs (bcka) clock should be input to dsd_sclk for phase modulation mode. (see figure 22 on page 26) when set to 1, the 64fs (bckd) clock should be input to dsd_sclk for phase modulation mode. 5.4.6 dsd phase modulation mode enable (dsd_pm_en) function: when set to 1, dsd phase modulation input mode is enabled and the dsd_pm_mode bit should be set accordingly. when set to 0 (default), this func tion is disabled (dsd normal mode). 5.5 filter control (address 05h) 5.5.1 interpolation filter select (filt_sel) function: when set to 0 (default), the interp olation filter ha s a fast roll off. when set to 1, the interpolat ion filter has a slow roll off. the specifications for each filter can be found in t he analog characteristics tabl e, and response plots can be found in figures 28 to 51 found on the page 26. 76543210 reserved reserved reserved reserved reserved reserved reserved filt_sel 00000000
CS4385 42 ds671a1 5.6 invert contro l (address 06h) 5.6.1 invert signal polarity (inv_xx) function: when set to 1, this bit inverts th e signal polarity of channel xx. when set to 0 (default), this function is disabled. 5.7 group control (address 07h) 5.7.1 mutec pin control(mutec) default = 0 0 - two mute control signals 1 - single mute control signal on mutec1 function: selects how the internal mute signals are routed to the mutec1 and mutec234 pins. when set to ?0?, a logical and of dac pair 1 mute control sign als are output on mutec1 and a logical and of the mute control signals of dac pairs 2, 3, and 4 are output on mutec234. when set to ?1?, a logical and of all dac pair mute cont rol signals is output on the mutec1 pin, mutec234 will remain static. for more information on the use of the mute control function see the mutec1 and mutec234 pins in section 3.11. 5.7.2 channel a volume = channel b volume (px_a=b) default = 0 0 - disabled 1 - enabled function: the aoutax and aoutbx volume levels are indepe ndently controlled by the a and the b channel vol- ume control bytes when this functi on is disabled. the volume on both aoutax and aoutbx are deter- mined by the a channel attenuation and volume cont rol bytes (per a-b pair), and the b channel bytes are ignored when this function is enabled. 5.7.3 single volume control (snglvol) default = 0 0 - disabled 1 - enabled 76543210 inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 reserved mutec reserved p1_a=b p2_a=b p3_a=b p4_a=b snglvol 00100100
CS4385 ds671a1 43 function: the individual channel volume levels are independent ly controlled by their re spective volume control bytes when this function is disabled. the volume on all channels is determined by the a1 channel volume control byte, and the other volume control by tes are ignored when this function is enabled. 5.8 ramp and mute (address 08h) 5.8.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is select ed all level changes will take ef fect immediately in one step. zero cross zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audi ble artifacts. the request ed level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero cros sing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to th e new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that sign al level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implement ed on a signal zero cr ossing. the 1/8 db level change will occur after a ti meout period between 512 and 1024 samp le periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enco unter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 5.8.2 soft volume ramp-up after error (rmp_up) function: 76543210 szc1 szc0 rmp_up rmp_dn pamute damute mute_p1 mute_p0 10000000
CS4385 44 ds671a1 when set to 1 (default), an un-mu te will be performed after executi ng a filter mode change, after a lrck/mclk ratio change or error, and after changing the functional mode. this un-mute is effected, sim- ilar to attenuation changes, by the soft and zero cros s bits in the volume and mixing control register. when set to 0, an immediate un-mute is performed in these instances. note: for best results, it is reco mmended that this feature be used in conjunction with the rmp_dn bit. 5.8.3 soft ramp-down before filter mode change (rmp_dn) function: when set to 1 (default), a mute will be performed prior to executing a f ilter mode change. this mute is effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate mute is performed prior to executing a filter mode change. note: for best results, it is reco mmended that this feature be used in conjunction with the rmp_up bit. 5.8.4 pcm auto-mute (pamute) function: when set to 1 (default) the digital -to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-st atic data will rele ase the mute. de- tection and muting is d one independently for each channel. the qu iescent voltage on the output will be retained and the mute cont rol pin will go active du ring the mute period. when set to 0 this function is disabled. 5.8.5 dsd auto-mute (damute) function: when set to 1 (default) the digital -to-analog converter output will mute following the reception of 256 re- peated 8-bit dsd mute patterns (as defined in the sacd specification). a single bit not fitting the repeated mute pattern (mentioned above) will release the mute. de tection and muting is done independe ntly for each channel. th e quiescent voltage on the output will be retained and the mute control pin will go acti ve during the mute period.
CS4385 ds671a1 45 5.8.6 mute polarity and detect (mutep1:0) default = 00 00 - auto polarity detect, selected from mutec1 pin 01 - reserved 10 - active low mute polarity 11 - active high mute polarity function: auto mute polarity detect (00) see section 3.11 on page 29 for description. active low mute polarity (10) when rst is low the outputs are high impedance and will n eed to be biased active . once reset has been released and after this bit is set, the mutec output pins will be active low polarity. active high mute polarity (11) at reset time the outputs are high impedance and will need to be bias ed active. once reset has been released and after this bit is set, the mutec output pins will be active high polarity. 5.9 mute control (address 09h) 5.9.1 mute (mute_xx) default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter ou tput will mute when enabled. the qu iescent voltage on the output will be retained. the muting function is affected, similarly to attenuation changes, by the soft and zero cross bits. the mute pins will go active during th e mute period according to the mutec bit. 76543210 mute_b4 mute_a4 mute_b3 mute_a3 mute_b2 mute_a2 mute_b1 mute_a1 00000000
CS4385 46 ds671a1 5.10 mixing control (address 0ah, 0dh, 10h, 13h) 5.10.1 de-emphasis control (px_dem1:0) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 20) de-emphasis is only available in single speed mode. 5.10.2 atapi channel mixing and muting (atapi) default = 01001 - aoutax=al, aoutbx=br (stereo) function: the implements the channel mixing functions of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 14 and figure 21 for additional information. 76543210 reserved px_dem1 px_dem0 pxatapi4 pxatapi3 pxatapi2 pxatapi1 pxatapi0 00101001 atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] table 9. atapi decode
CS4385 ds671a1 47 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 01111 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(bl+ar)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(al+br)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx table 9. atapi decode
CS4385 48 ds671a1 5.11 volume control (address 0bh, 0ch, 0eh, 0fh, 11h, 12h, 14h, 15h) these eight registers provide individual volume and mute control for each of the eight channels. the values for ?xx? in the bit fields above are as follows: register address 0bh - xx = a1 register address 0ch - xx = b1 register address 0eh - xx = a2 register address 0fh - xx = b2 register address 11h - xx = a3 register address 12h - xx = b3 register address 14h - xx = a4 register address 15h - xx = b4 5.11.1 digital volume control (xx_vol7:0) default = 00h (0 db) function: the digital volume control registers allow independent control of the si gnal levels in 1/2 db increments from 0 to -127.5 db. volume settings are decoded as shown in table 15. the volume changes are imple- mented as dictated by the soft and zero cross bits in the power and muting control register. note that the values in the volume setting column in table 15 are approximate. the actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. 5.12 pcm clock mode (address 16h) 5.12.1 master clock divide by 2 enable (mclkdiv) function: when set to 1, the mclkdiv bit enables a circuit wh ich divides the externally applied mclk signal by 2 prior to all other internal circuitry. when set to 0 (default), mclk is unchanged. 76543210 xx_vol7 xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 table 10. example digital volume settings binary code decimal value volume setting 00000000 0 0 db 00000001 1 -0.5 db 00000110 6 -3.0 db 11111111 255 -127.5 db 76543210 reserved reserved mclkdiv reserved r eserved reserved reserved reserved 00000000
CS4385 ds671a1 49 6. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to- noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distor tion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries asso ciation of japan , eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 7. references 1. "how to achieve optimum performance from delt a-sigma a/d & d/a conver ters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2. cdb4385 evaluation board datasheet 3. ?design notes for a 2-pole filter with differential input? by steven gr een. cirrus logic application note an48 4. ?the i 2 c-bus specification: version 2.0? ph ilips semiconductors, december 1998. http://www.semicondu ctors.philips.com
CS4385 50 ds671a1 8. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
CS4385 ds671a1 51 9. appendix 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 28. single speed (fast) stopband rejection figure 29. single speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 30. single speed (fast) tran sition band (detail) figure 31. single speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 32. single speed (slow) stopband reject ion figure 33. single speed (slow) transition band
CS4385 52 ds671a1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 34. single speed (slow) transition band (d etail) figure 35. single speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 36. double speed (fast) stopband rejection figure 37. double speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 38. double speed (fast) transition band (detail) figure 39. double speed (fast) passband ripple
CS4385 ds671a1 53 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 40. double speed (slow) stopband rejectio n figure 41. double speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 42. double speed (slow) transition band (d etail) figure 43. double speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 44. quad speed (fast) stopband rejection figure 45. quad speed (fast) transition band
CS4385 54 ds671a1 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 46. quad speed (fast) transition band (d etail) figure 47. quad speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 48. quad speed (slow) stopband rejectio n figure 49. quad speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 50. quad speed (slow) transition band (detail) figure 51. quad speed (slow) passband ripple
CS4385 ds671a1 55 table 11. revision history contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contac ts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts important notice "advance" product information describes products that are in development and subject to development changes.cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant informati on to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirru s for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of th ird parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives co nsent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage ("critical applications"). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, life support products or other critical applications (including medical devices, aircraft s ystems or components and persona l or automotive safety or se- curity devices). inclusion of cirrus produc ts in such applications is understood to be fully at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or implied, including the implie d warranties of merchantability and fitness for particular purpos e, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus products in critical applications, cu stomer agrees, by such use, to fully indemnify cirrus, its office rs, directors, employees, distri butors and other agents from any and all liability, includ- ing attorneys' fees and costs, that may result from or arise in connection with these uses. purchase of i 2 c components of cirrus logic, inc., or one of its sublicensed associated companies conveys a license under the phillips i 2 c patent rights to use those components in a standard i 2 c system. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. release date changes a1 oct 2004 initial release
CS4385 56 ds671a1

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